Image: ExecutableFix

AMD’s upcoming family of Zen 4-based Ryzen 7000 Series processors (code name “Raphael”) will be some of the first to leverage red team’s new AM5 platform, which switches out its predecessor’s PGA (pin grid array) design for an LGA (land grid array) one that shifts the pins over to the socket (LGA 1718). According to new renders shared by leaker ExecutableFix, these chips will also introduce a brand-new IHS (integrated heat spreader) design that replaces the traditional square metal lid with one that features multiple notches and cutouts. It isn’t yet clear what prompted AMD to redesign the exterior cover for its Zen 4 processors so significantly.

AMD CPUs for AM5 socket would allegedly support dual-channel DDR5 memory as well as PCIe Gen4.0. This means that there would no Gen5 support and that would remain exclusive to Alder Lake-S, at least for the time being. The Raphael CPUs will have 28 PCIe lanes, which is an upgrade of 4 compared to Zen3 CPUs. At this time, AMD is planning 120W CPUs for this socket, but there are allegedly plans for 170W SKUs as well.

Sources: ExecutableFix, VideoCardz

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6 Comments

  1. Interesting.

    I wonder if they are finally going to start stacking silicon like in HBM, and they need extra space?

  2. I wonder if they are increasing surface area for better mating of heatsink and heatspreader. Perhaps thermal transference from chip to heatsink is improved by this design?

  3. Looking at the design I wonder if contact areas for heat transfer are also on the sides. Meaning a heat sink would need to effectively ‘grip’ the ihs. I could see thst mechanically giving them more surface area for heat transfer and let them ‘wrap’ around the chips on the board for more direct heat transfer there. But.. man that would make delidding a huge nono.

  4. Last I checked, AMD was using solder to mate the heatspreader to the core surfaces. Generally, I had heard de-lidding the heat spreader was much higher risk and not particularly helpful for better temps on ryzen processors for this reason.

  5. Increasing
    [QUOTE=”CVNet1, post: 35174, member: 59″]
    I wonder if they are increasing surface area for better mating of heatsink and heatspreader. Perhaps thermal transference from chip to heatsink is improved by this design?
    [/QUOTE]
    Increasing the surface area is tantamount to going back a node, removing the benefits of a smaller die size, making it tricky for a node shrink to be of any use.
    This requires good enough silicon quality for a higher node but only with the benefit of a lower node, it makes no sense.
    There is always going to be a power (watts) vs silicon area issue with a node change.
    No direct way around that exists, it has to be considered in the die shrink design.
    My belief is, direct die contact (or as close as) with the heatsink must at some point become the norm, otherwise die shrinks will need to produce much less power to use existing mainstream heatsink tech due to the much smaller contact surface area.
    Yet we are seeing increased power use with smaller dies.

  6. [QUOTE=”Zarathustra, post: 35166, member: 203″]
    Interesting.

    I wonder if they are finally going to start stacking silicon like in HBM, and they need extra space?
    [/QUOTE]

    Do I get to say “[URL=’https://amp.hothardware.com/news/amd-zen-4-demos-stacked-3d-v-cache’]I called it[/URL]”?

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