Image: Intel

Enthusiasts who are planning to make the jump to Intel’s Alder Lake flagship might want to hold off for a little bit, as there’s indication that blue team will be unveiling an even better version in the very near future.

That’s according to sources with VideoCardz, which claim that a Core i9-12900KS is already being tested by board partners. The new model is said to be a pre-binned SKU that features an all-core boost of 5.2 GHz, a notable improvement over the current Core i9-12900K flagship.

“It is basically a pre-binned SKU with an all-core (Performance core) boost at 5.2 GHz, so 200 MHz higher than 12900K,” VideoCardz explained. “This frequency heavily depends on a workload, and most reviews have shown that stock 12900K reaches around 4.85-4.9 GHz all-core boost, which is why the 12900KS should easily offer 5.0 GHz out of the box.”

As noted by VideoCardz, Intel hasn’t released a KS version of its processors since the Core i9-9900KS, a 9th-gen Coffee Lake CPU that was released in October 2019. The speculation is that Intel’s Core i9-12900KS was designed to go up against AMD’s upcoming Ryzen chips with new 3D V-Cache technology, which promises substantially higher gaming performance.

Source: VideoCardz

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10 Comments

  1. So, ALL cores, or just the 8 big cores? :p

    This is getting confusing.

    Still, only 20 PCIe lanes means I will never own one of these.

    I don’t feel like building two PC’s, one for productivity and one for games, so I need my one CPU to be able to do it all, and that includes a large number of PCIe lanes. I’d say an absolute minimum of 40.

  2. [QUOTE=”Zarathustra, post: 45285, member: 203″]
    Still, only 20 PCIe lanes means I will never own one of these.
    [/QUOTE]
    28 but that’s still a bit low for you then

  3. [QUOTE=”Zarathustra, post: 45285, member: 203″]
    So, ALL cores, or just the 8 big cores? :p

    This is getting confusing.

    Still, only 20 PCIe lanes means I will never own one of these.

    I don’t feel like building two PC’s, one for productivity and one for games, so I need my one CPU to be able to do it all, and that includes a large number of PCIe lanes. I’d say an absolute minimum of 40.
    [/QUOTE]
    Total 12th generation/Z690 platform lane count is 48.

  4. [QUOTE=”Dan_D, post: 45294, member: 6″]
    Total 12th generation/Z690 platform lane count is 48.
    [/QUOTE]

    [URL=’https://ark.intel.com/content/www/us/en/ark/products/134599/intel-core-i912900k-processor-30m-cache-up-to-5-20-ghz.html’]Ark.intel.com says 20?[/URL]

    [Code]
    Max # of PCI Express Lanes: 20[/code]

  5. [QUOTE=”Zarathustra, post: 45299, member: 203″]
    [URL=’https://ark.intel.com/content/www/us/en/ark/products/134599/intel-core-i912900k-processor-30m-cache-up-to-5-20-ghz.html’]Ark.intel.com says 20?[/URL]

    [Code]
    Max # of PCI Express Lanes: 20[/code]
    [/QUOTE]
    That’s why I said total platform. The chipset has several as well. They don’t all need to be on the CPU, especially given that the DMI 4.0 link now has 8x lanes for bandwidth. Generally more than enough bandwidth for the vast majority of devices.

    [ATTACH type=”full”]1372[/ATTACH]

  6. [QUOTE=”Dan_D, post: 45301, member: 6″]
    That’s why I said total platform. The chipset has several as well. They don’t all need to be on the CPU, especially given that the DMI 4.0 link now has 8x lanes for bandwidth. Generally more than enough bandwidth for the vast majority of devices.

    [ATTACH=full]1372[/ATTACH]
    [/QUOTE]

    Ahh, they seem to have changed how they count lanes then, because the max number of lanes used to include the chipset uplinks.

    Since this gen is PCIe gen 5 compatible they could technically have the chipset function as a PLX chip and provide a larger number of lower gen lanes, but that would likely introduce latencies.

  7. [QUOTE=”Zarathustra, post: 45303, member: 203″]
    Ahh, they seem to have changed how they count lanes then, because the max number of lanes used to include the chipset uplinks.

    Since this gen is PCIe gen 5 compatible they could technically have the chipset function as a PLX chip and provide a larger number of lower gen lanes, but that would likely introduce latencies.
    [/QUOTE]
    Minimal. I’ve done the testing with PLX chips so many times and found that it amounted to a difference that you could chalk up to run to run variances provided it wasn’t a consistent and reproduceable variable. In games the differences has only ever been 1-3FPS in anything I’ve tested. People blow the latency increase way out of proportion as most people would never notice it without reviewers showing them the data.

  8. [QUOTE=”Dan_D, post: 45304, member: 6″]
    Minimal. I’ve done the testing with PLX chips so many times and found that it amounted to a difference that you could chalk up to run to run variances provided it wasn’t a consistent and reproduceable variable. In games the differences has only ever been 1-3FPS in anything I’ve tested. People blow the latency increase way out of proportion as most people would never notice it without reviewers showing them the data.
    [/QUOTE]

    I thought you guys had done a test on using a NVMe drive in a secondary slot coming off the chipset, and if I recall properly, there was a surprisngly large performance impact. Much larger than I had expected before reading the article. I will have to go look it up again.

  9. [QUOTE=”Zarathustra, post: 45312, member: 203″]
    I thought you guys had done a test on using a NVMe drive in a secondary slot coming off the chipset, and if I recall properly, there was a surprisngly large performance impact. Much larger than I had expected before reading the article. I will have to go look it up again.
    [/QUOTE]

    SSD’s in a benchmark test may very well show a difference. However, most devices do not need the same kind of bandwidth. That said, I wouldn’t worry about it as SSD’s do not typically place that much demand on the bus either. The benchmarks are synthetic tests designed to maximize read and write loads to gauge performance. It does not simulate real world conditions.

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