AMD Zen 5 “Strix” APU Features Performance and Efficiency Cores

Image: AMD

AMD appears to be taking a page out of Intel’s playbook with “Strix,” a new Zen 5 APU that’s apparently in development. According to CPU-Z screenshots shared by, this CPU will feature a mix of Performance and Efficiency cores, echoing a design that Intel introduced for its more recent Core processors. AMD had suggested in the past that it didn’t really care for Intel’s hybrid core approach.

The next-gen APU, codenamed “Strix,” is built on a 4nm Process and features the Big.Little CPU architecture with 4 Performance Cores and 8 Efficiency Cores. Both the P and E cores support hyper-threading. On the P Core and E Core, the L1 Data cache is 48 kb, while the L1 instruction cache is 32kb. Each P Core boasts 1Mb of cache, and with E cores, it looks like there are 4 in a group, sharing 1mb of L2 Cache. This setup is quite similar to Intel’s design. Keep in mind, it’s still in the ES stage, so there’s more to come. We’ll keep you posted on any further updates!


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