PCI-SIG, the electronics industry consortium behind the ubiquitous PCI standard, has announced that the first official draft of the PCIe Gen 7 specification is now available for members to download, and with it comes the confirmation that PCIe 7.0 remains on track for full release next year, in 2025. The new specification is headlined by its aim of delivering 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration.
PCIe 7.0 goals include:
- Delivering 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration
- Utilizing PAM4 (Pulse Amplitude Modulation with 4 levels) signaling
- Focusing on the channel parameters and reach
- Continuing to deliver low-latency and high-reliability targets
- Improving power efficiency
- Maintaining backwards compatibility with all previous generations of PCIe technology
An overview of previous PCIe generations:
PCI-SIG noted:
This is the official first draft of the specification, incorporating all the feedback we received from members after the release of Version 0.3 in June 2023.
PCIe 7.0 technology is aimed to be a scalable interconnect solution for data-intensive markets like 800G Ethernet, Artificial Intelligence/Machine Learning, Hyperscale Data Centers, HPC, Quantum Computing and the Cloud. As PCIe technology continues to evolve to meet the high bandwidth demands of these applications, the PCIe 7.0 architecture will focus on channel parameters and reach while improving power efficiency.