PC users are chomping at the bit to get an official update from AMD regarding Olympic Ridge, but ongoing rumors suggest good things are on the horizon. Whether it be a new X3D or non-X3D part, or single versus dual CCD package, there are some folks who can’t wait to hear what’s in store for AMD’s Zen6 lineup. Well, the good news is that rumors regarding it have remained consistent for some time, so perhaps the time until an official reveal is narrowing down. The latest comes via a well-known hardware info leaker, HXL, who has provided a few more details, although MLID has asked if their 2-year-old post is the source of this rumor.
According to HXL (via VideoCardz), there will be a Zen6 non-X3D processor featuring a single 12-core CCD with 48MB L3 cache built using TSMC’s N2 process at a die size of 76mm². This core count and L3 cache are a 50% increase over Zen5 non-X3d offerings and are expected to compete with Intel’s Core Ultra 400 Nova Lake-S processors, which focus on large last-level cache designs.
Is the source my leak from 2 years ago? 🤔https://t.co/7sOHOjkST4 pic.twitter.com/kD40iJPn0Q
— Moore's Law Is Dead (@mooreslawisdead) January 30, 2026
Other rumors claim that a Zen6 12-core single CCD X3D variant will follow a similar 50% upscale with 144MB L3 cache, and a Dual CCD version could have up to 288 MB L3 shared between both CPU core complexes. AMD has yet to confirm any of this, including the “Olympic Ridge” code name, but hopes are high that it will give details soon. It is also wondered if it will continue with the current product numbering schema and proceed to the Ryzen 10000 series, or perhaps change things up. In either case, curiosity for a Next-Gen Ryzen lineup is on the rise as folks wonder what new technologies AMD has up its sleeve.
Discussion (19 replies)
Join Discussion →This would be fun to see... that and a 24 core 42 thread desktop processor.
I'd love a 12 core single CCD X3D processor.
That's what the leakers/whateveryouwannacallem over on AT have been saying for months. The 12c CCD will be on an N2-class node, but there will be mobile CCDs on N3P that have Zen6c cores as well. I don't have all the configurations memorized. Some SKUs will mix N2 and N3P CCDs, including Medusa Halo.
Same!
zen 7 will have 16 core CCDs
10900X/X3D with 40 threads (two CCDs with 10 cores each) should end the x900X/x900X3D low sales volume curse that AMD has had to deal with so far, due to six cores per CCD not being good enough for gaming.
Dang man, you lost 6 threads in that calculation. Maybe you should have ran it by AI first to find your mistake. LOL
All jokes aside, I am very interested in this. Especially if L3 cache scales with number of cores.
That 24 core, 48 thread processor with 96MB of L3 cache would be freaking awesome. And a X3D part with even more. Oh yes baby. Give me!
Uhhh I was subtracting some for NPU's... yea.... that's the ticket!
What AMD really needs to focus on in the next generation is improving the fabric bandwidth situation so that it is no longer a bottleneck for RAM and PCIe bandwidth and latency.
Hard pass if it comes with an NPU.
At least unless it can be disabled in the BIOS.
I feel like the many core consumer desktop thing is so overplayed at this point.
It was never interesting when it was new when Bulldozer first came out with 8 cores, and it isn't interesting today. Large numbers of cores are great for servers, especially hypervisors, and also for rendering/encoding type workstations, but for most desktop use they are utterly useless.
Especially since with dual channel RAM, the RAM bandwidth increasingly becomes the bottleneck with all of those cores vying for it.
Even our current 16 core top end consumer CPU's are probably too much for dual channel RAM.
The really interesting development here is not the potential for crazy core dual die consumer chips, but rather the 12 core variant with a single X3D cache that doesn't suffer from needing to get core parking right.
They need to be focusing much more on per thread performance, not just the cop out that is throwing more useless cores at CPU's. And to that end they need to solve the RAM latency and bandwidth limitation that the fabric connection to the I/O die causes.
I think chiplets are great, but we need them to communicate better. The fabric needs to be twice or three times as fast. Maybe that can be achieved through dual links or something? Instead of one 2000Mhz fabric link, what if we had dual 3000Mhz links?
Problem is, AMD likes keeping costs low. Zen 6 probably already has a new IOD but whatever enhancements they have made to it, we'll be stuck with that IOD till Zen 7 or even Zen 8. I could see them doing a 3000 MHz fabric but not dual ones. They don't care that much because Intel isn't competing like they should to force AMD to make better stuff. And the only way I see Intel forcing AMD's hand is to have their Nova Lake mainstream parts deliver at least +10% performance uplift over 14900KS in gaming.
Oh, you are probably right. I expect Zen6 to be an evolutionary improvement rather than a revolutionary one.
Fabric may be entirely internal to the CPU package, but it requires a lot of hooks in the BIOS, and if they mess too much with how the I/O Die communicates with the RAM, it may no longer be fully compatible with the AM5 pinout, voltage and current specs.
And even if it is, if you need to rewrite the BIOS too much to make it work, we are going to be right back in the bad place we were with AM4 needing a different BIOS for earlier CPU releases than for later CPU releases even if the motherboard is the same hardware-wise. I know AMD would rather avoid that if they have the choice, and if they aren't seeing too much pressure from Intel on the gaming front, they have no incentive to make their lives more difficult.
I haven't read any of the Panther Lake reviews/previews yet, but it looks like Intel is pushing for some pretty high official RAM clocks for them. I recently read a headline saying something about them targeting a minimum of DDR5 with 7467 MT/s minimum to allow partners to use for their Arc B series iGPU branding on Panther Lake systems. Of course, that's with the iGPU sharing the main system RAM which causes resource constrictions, so...
But back to AMD.
I can't speak at all to the cores per die thing, but I do expect them to nudge up the Fclk a bit, and maybe launch a new chipset that finally connects to the CPU using PCIe5, which might provide us more downstream options for chipset PCIe lanes for either PCIe slots or m.2 drives.
I did just invest in a Zen5 build I am not done building yet, but I'd totally welcome that.
Someone shared this:
No idea about the source but if that's true, that's a pretty big jump for the NGU. That thing doesn't go above 34x for my 245KF so default being 55x in Panther and hopefully Nova Lake is going to be a big step in the right direction.
I'm not going to lie.
I have absolutely no idea what anything in that chart means 😅