Image: NVIDIA

NVIDIA and AMD’s next-generation flagship graphics cards, which are expected to leverage the Lovelace and RDNA 3 architectures, respectively, could be more power hungry than anyone might have imagined. This is according to the latest rumors from prominent leakers such as kopite7kimi, who recently commented on speculation about NVIDIA’s flagship GeForce RTX 40 Series products featuring a TDP of at least 400 watts. While that specification already exceeds the GeForce RTX 3090’s 350-watt TDP by a notable amount, kopite7kimi suggested that the TDP for the flagship models will go even higher, stating that “400 is not enough.” As for AMD, Beyond3D forum member and alleged insider Bondrewd recently shut down speculation that Navi 31 could draw as much as 500 watts. That prompted 3DCenter.org to seek out a more probable estimate by looking into the supposed size of the GPU and its components, which led to a potential TBP of 420 to 450 watts.


AMD Navi 31NVIDIA AD102
ChipTSMC 5nm, MCM, total probably ~ 800mm² (or more)TSMC 5nm, monolithic, probably ~ 600mm²
Hardware6 SE, 60 WGP, 15’360 FP32, Infinity Cache, 256 bit GDDR612 RE, 144 SM, 18’432 FP32, 384 bit GDDR6X
Power Consumptionprobably in the direction of 450-480 wattsprobably in the direction of 420-450 watts
Source: 3DCenter.org

This is not entirely surprising, because the graphics chip developers are fighting against two effects: On the one hand, the advances in semiconductor production are not geared towards achieving a power consumption effect equal to the gain in space. If you use the area gain (fully), the result is always a slightly higher power consumption – usually with a greater difference than what you could make up for by improving efficiency at the architecture level. And on the other hand, AMD & nVidia are approaching the 5nm generation, as is well known, with violent hardware jumps – which are generally impossible to achieve with the same power consumption.

Sources: kopite7kimi, Bondrewd (via 3DCenter.org)

Don’t Miss Out on More FPS Review Content!

Our weekly newsletter includes a recap of our reviews and a run down of the most popular tech news that we published.

Join the Conversation

12 Comments

  1. Yeah, back before 32nm power use used to scale almost perfectly linearly with node size, all else being equal.

    Ever since 32nm that scaling has become worse and worse. There is still a node to node benefit, but it is much smaller than it used to be.

    Pesky sub-atomic effects…

  2. [QUOTE=”Zarathustra, post: 38650, member: 203″]
    Yeah, back before 32nm power use used to scale almost perfectly linearly with node size, all else being equal.

    Ever since 32nm that scaling has become worse and worse. There is still a node to node benefit, but it is much smaller than it used to be.

    Pesky sub-atomic effects…
    [/QUOTE]
    That could decide to devote a node to power savings instead of performance. Can you imagine the whining though if the 40X0 line had the same performance, but half the power draw?

  3. [QUOTE=”Zarathustra, post: 38650, member: 203″]
    Yeah, back before 32nm power use used to scale almost perfectly linearly with node size, all else being equal.

    Ever since 32nm that scaling has become worse and worse. There is still a node to node benefit, but it is much smaller than it used to be.

    Pesky sub-atomic effects…
    [/QUOTE]
    I gotta wonder if such a comparison could even be [I]made [/I]today. You’d never be able to keep enough of the variables in check to really say, right?

    Not that it didn’t at least seem like power draw could drop node-to-node in a somewhat linear fashion. Just that complexity continues to skyrocket alongside transistor shrinks.

    Also that the power envelopes are targeted. End users may not really be deterred by an extra power lead outside of the SFF realm, but I’d bet OEMs sure do, especially when it comes to mobile parts! I expect there to be solid market incentives for GPU manufacturers to target specific power consumption bands, limiting or bolstering just how much they take advantage of new process nodes, which will also distort our perception of the efficiency gains.

  4. [QUOTE=”Endgame, post: 38658, member: 1041″]
    That could decide to devote a node to power savings instead of performance. Can you imagine the whining though if the 40X0 line had the same performance, but half the power draw?
    [/QUOTE]
    There are separate nodes for power saving versus high performance. It’s just they don’t tend to clock up very well.

  5. The move to 5nm TSMC (if true) will massively improve perf/watt over their current node.

    NVIDIA will be going from 44.56 million transistors per mm² to 173 million transistors per mm²

    This rumor is likely the A100 replacement and that already has a TDP of 400 watts so this is not really even news.

  6. [QUOTE=”Endgame, post: 38658, member: 1041″]
    That could decide to devote a node to power savings instead of performance. Can you imagine the whining though if the 40X0 line had the same performance, but half the power draw?
    [/QUOTE]

    There would certainly be applications for that, especially in mobile or compact/quiet systems, but personally I’ll take raw brute power over anything else for my desktop.

    I have a pretty beefy custom water loop though :p

  7. [QUOTE=”Zarathustra, post: 38696, member: 203″]
    There would certainly be applications for that, especially in mobile or compact/quiet systems, but personally I’ll take raw brute power over anything else for my desktop.

    I have a pretty beefy custom water loop though :p
    [/QUOTE]
    I would just take something I could buy

  8. [QUOTE=”Brian_B, post: 38701, member: 96″]
    I’m wondering if 420 is a happy coincidence, or just happy.
    [/QUOTE]
    PCIe power usually iterates in 75w increments – so 375W and 450W would make sense.

    Maybe the rumormongers were… smoking something?

    😎

  9. [QUOTE=”kcthebrewer, post: 38677, member: 498″]
    The move to 5nm TSMC (if true) will massively improve perf/watt over their current node.

    NVIDIA will be going from 44.56 million transistors per mm² to 173 million transistors per mm²
    [/QUOTE]
    So this really has me thinking. They could basically build 3090 performance at 1/4 of the die size. I would actually love to see a tick generation – same performance as the 3090, but dramatically more supply.

  10. I’d be all for that as well just a generational improvement on power and efficiency. Let more people into that tier of performance.

Leave a comment