PCI-SIG, the group behind the hugely relevant PCI Express standard, has announced that PCIe 6.0 is one step closer to final release. PCIe 6.0 will double the bandwidth of the PCIe 5.0 specification, enabling 64 GT/s data rates and up to 256 GB/s via x16 configurations. It will also feature a type of error correction that allows for improved bandwidth efficiency.
Per PCI-SIG:
I am excited to report that PCI-SIG has released PCIe 6.0 specification, version 0.9 to our members. This is a major milestone in our continued effort to double the data rate of the PCI Express specifications while maintaining backwards compatibility. Thanks to the hard work and dedication of the technical members of our protocol and electrical workgroups, we were able to reach this achievement two years after we announced the PCIe 6.0 specification in June 2019. The PCIe 6.0 specification, version 0.9 is the final draft of the specification wherein members perform internal reviews of the technology for their essential patents. No additional functional changes are expected during this time.
PCIe 6.0 specifications:
- 64 GT/s data rate and up to 256 GB/s via x16 configuration, doubling the bandwidth of the PCIe 5.0 specification
- PAM-4 (Pulse Amplitude Modulation with 4 levels) encoding and leverages existing 56G PAM-4 in the industry
- FLIT (flow control unit)-based encoding
- Low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
- Backwards compatibility with all previous generations of PCIe technology
Intel’s Alder Lake platform will be the first to introduce PCIe 5.0 to the mainstream. PCI-SIG says that it’ll be sharing more about PCIe 6.0 later this year.
Source: PCI-SIG