TSMC Announces N4P Process, 22 Percent Improvement in Power Efficiency versus N5

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Image: TSMC

TSMC today introduced its N4P process, the third major enhancement of its 5 nm family for extending the performance, power efficiency, and density leadership of the platform. Described as a performance-focused enhancement, N4P offers a 11 percent performance boost over TSMC’s original N5 technology. It also offers an impressive 22 percent improvement in power efficiency over N5, as well as a 6 percent improvement in transistor density.

From TSMC:

TSMC customers often invest precious resources to develop new IP, architectures, and other innovations for their products. The N4P process was designed for an easy migration of 5nm platform-based products, which enables customers to not only better maximize their investment but will also deliver faster and more power efficient refreshes to their N5 products.

“With N4P, TSMC strengthens our portfolio of advanced logic semiconductor technologies, each with its unique blend of performance, power efficiency and cost. N4P was optimized to provide a further enhanced advanced technology platform for both HPC and mobile applications,” said Dr. Kevin Zhang, Senior Vice President of Business Development at TSMC. “Between all the variants of N5, N4 and N3 technologies, our customers will have the ultimate flexibility and unmatched choice of the best mix of attributes for their products.”

Source: TSMC

Tsing Mui
News poster at The FPS Review.

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