Introduction
AMD has not yet announced its next-generation (Zen 6-based) DIY Desktop CPUs; however, AMD has just launched its next-generation server AMD EPYC 9006 6th-generation “Venice” CPUs, which are based on the Zen 6 architecture! In this way, we can get an early preview of what the architecture looks like in the upcoming Zen 6 desktop CPUs (though not the specific SOCs or configurations).
As we await the launch of the desktop CPUs, AMD is moving full-force in the server and enterprise markets with its next-generation CPUs, which supersede AMD’s EPYC “Turin” 5th Generation CPUs. We’ll go over some of the information about the new EPYC CPUs, but our main focus will be on the Zen 6 architecture itself, which will play a part in the upcoming desktop CPU release.
EPYC CPU Leadership & Venice Intro
To understand the new EPYC CPUs, we need to understand that the previous generation of EPYC was AMD’s 5th Generation, with the codename of “Turin.” What AMD is specifically launching now is the 6th Generation of EPYC CPUs with the codename of “Venice.” It is Venice that is based on the new Zen 6 architecture, whereas Turin was based on the Zen 5 architecture.
While Turin was designed with AI optimization in mind, Venice is ready for the Agentic AI era. The series of CPUs will fall under the AMD EPYC 9006 server CPUs. Performance improvements are shown with 2.0x improvement in integer compute, 2.4x improvement in floating-point, 2.7x in memory bandwidth, 1.4x in HPC compute, and 1.3x performance in matrix compute compared to the previous CPUs.
The AMD EPYC CPUs fall into an ecosystem of AMD hardware for end-to-end AI compute, with AMD Instinct GPUs, Pensando Networking, Ryzen AI and Radeon AI, Versal Adaptive SOCs, and AMD ROCm software. AMD’s EPYC “Venice” CPUs were designed to provide more work per Watt, higher density with 256 cores and 512 threads, higher throughput, reduced memory costs with MEXT, and diversity in SKUs.
AMD Zen 6 Architecture
At the heart of the AMD EPYC “Venice” 6th Generation CPUs is the brand-new Zen 6 architecture. This is the same architecture that will be used for AMD’s next-generation desktop CPUs that we are all looking forward to in 2027. Though configuration, SOCs, and SKUs will be different, the base underlying architecture should be the same, if not extremely similar.
For the server CPUs, the Zen 6 family core design objective was geared toward the Agentic Era in many ways. It was designed to deliver a major core performance increase, leverage efficient design for maximum throughput, enhance AI capability, improve for the lowest latency, and improve compute abilities.
As we have seen with previous AMD CPU designs, there are “c” processors, in this case “Zen 6c” processor cores. In typical fashion for AMD, the “c” CPUs have the same capabilities as their bigger brothers; no functionality is lost, only that they run in a different power configuration. In order to cram as many as 256 cores into the package, the highest-end will be made up of the Zen 6c cores.
A single Zen 6c “core” consists of a two-basic-block fetch and pipeline with 8-wide dispatch/rename, 6 ALUs, 4 Loads/2 Stores, and a 512-bit FP Datapath with 2-cycle FADD, 64-byte fills/victim, and a 48K Data Cache. The improvements involve a larger OP-cache, a larger Return Address Stack, larger FP/INT schedulers, larger Load/Store Queues, a larger Reorder Buffer, increased OP Fusion, reduced Branch Misprediction Latency, and 4x VNMI INT8 pipes. You will notice the L1 Cache consisting of 32KB of 8-way, 32B fetch x2, and an L1D Cache of 48KB 12-way, 4 read, 2 write, 64B fill, 64B victim. You will notice the L2 Cache as a 1MB 16-way cache.
In the Zen 6 architecture, you will find optimized branch prediction, fetch, and Dispatch. The Branch Prediction tables have been optimized, there’s a larger return address stack of 64 entry, larger Branch Prediction Queues. The front-end latency and bandwidth are improved with 64B/cycle fetch, optimized 2-instruction fetch streams, a larger OP cache, and a max of 18 op delivery per cycle with an 8-wide dispatch.
Schedule and Execute block is also improved with a 96 shared ALU/AGU and a 48-wide dedicated ALU. Bandwidth is improved in the load/store and cache with larger load and store windows as well. There is increased management for a large thread count.
If you look at how Zen 5 and Zen 5c compare to Zen 6 and Zen 6c, we can start to see the improvements. We do find that some things have not changed, however. For example, AVX-512, FMUL/FMAC+FADD, and FMAC/FMUL/FADD latency is the same on Zen 6 and Zen 6c. We can also see that VNNI-INT16, BFLOAT16, and FP Store Bandwidth is the same on Zen 6 and Zen 6c.
Where they differ is that FP16 is now a full AVX-512 FP16 Compute. Bit Matrix Multiply Instructions have now been added. VNNI-INT8 increases to 4 pipes, FP schedulers increase to 3×46+, and FP Load/Store Bandwidth changes. to 2 512b or 4 256b loads. We do see that in the Zen 6c 32-Core Cache Hierarchy there is a 128M L3 16-way Cache.
Zen 5c to Zen 6c and Zen 5 to Zen 6 Comparison
The Zen 6c family is also optimized for the SOC. Yep, the cores in the complex have increased! (for the EPYC CPUs). Instead of 16 cores per complex in Zen 5c, Zen 6c will have 32 cores per complex! Maybe good news for an increase in the desktop side as well? This literally doubles the number of cores per complex. This then quadruples the cache in the complex, with 4M L3 cache per core compared to 2M previously.
The total L3 cache size increases to 128MB compared to 32MB! There is a higher maximum frequency as well, the new EPYC Venice CPUs can reach 4.1GHz compared to 3.7GHz on the previous CPUs, so that’s a nice increase. In return, the maximum number of cores increases from 192 cores to 256 cores!
Regarding the Zen 6 (non-C) CPU cores for the server EPYC CPUs, we also see a core increase per core complex (CCX)! Yep, that’s right; it says it right here: AMD is increasing from 8-Cores in each CCX up to 12 per CCX for the bigger Zen 6 cores on the EPYC CPU lineup. This improves the maximum possible cores from 64 up to 96 with the new EPYC CPUs.
The maximum frequency also increases from 5GHz up to 5.3GHz. L3 cache per core remains the same, but overall L3 Cache increases from 32MB to 48MB. This regular Zen 6 is the most interesting, as far as we are concerned, for the desktop CPU potential. This shows that AMD DOES have a 12-Core CCX configuration available this generation. Let’s see if that trickles down to the desktop CPUs now.
AMD EPYC 9006 “Venice” SOCs
Above, you can see an overview of the Venice SP7 6th Gen AMD EPYC SOC. There are variants with Zen 6 and Zen 6c cores. With Zen 6, you can have each CCD have 12 Cores, and up to 8 CCDs. This in turn gives us a total configuration of up to 96-Core/192-Thread. With the Zen 6c CCD, you can have up to 32 Cores per CCD and up to 8 CCDs.
This allows a total configuration of up to 256-Core/512-Thread. There is 1MB L2 Cache per Core and up to 128MB of L3 Cache. There will be a “Venice-X” CPU that utilizes 3D V-Cache and 1152MB of L3 Cache! These CPUs also use AMD’s 5th-generation Infinity Fabric. It does look like there are I/O die improvements here as well.
The SP7 socket platform itself has a new compact socket infrastructure measuring 76mm x 80mm. It supports faster I/O using up to PCIe Gen 6, 16Ch DDR5. It has up to 3 links of 64Gbps Gen 5 Infinity Fabric. On the memory side, it supports 16-channel DDR5 with ECC up to 8000MT/s (RDIMM). It supports MRDIMM speeds up to 12.8GT/s. It can support 1, 4, 8, 12, and 16-channel memory interleaving and up to 1.6TB/s of socket bandwidth.
The 2P platform has up to 128 lanes of PCIe Gen 6 speeds up to 64Gbps per lane and up to 16 bonus PCIe Gen 4 lanes. The 1P platform has up to 96 lanes of PCIe Gen 6 speeds at 64Gbps per lane and up to 8 bonus lanes of PCIe Gen 4.
Where the SP7 socket is geared for the highest performance and scale-out, there will be a more cost-effective SP8 socket for AMD EPYC “Venice” 6th-gen CPUs as well. On the SP8 platform, you can still get up to 8 CCDs of Zen 6 cores for up to 96-Cores/192-Threads.
However, it only supports up to 4 CCDs of Zen 6c cores for up to 128-Core/256-Thread configuration for Zen 6c. It also uses 5th Gen Infinity Fabric. The socket size is different, at a more compact 62.5mm x 80mm size. It does still support PCIe Gen 6, but 8Ch DDR5 at the maximum. It has up to 2 links of 64Gbps Gen 5 Infinity Fabric, but also 2P and 1P configurations.
On the memory side, SP8 supports 8-channel DDR5 at up to 8000MT/s (RDIMM). Therefore, 1, 4, and 8-channel memory interleaving and up to 2 DIMMs/Channel support. In the 2P config, it supports up to 192 Lanes of PCIe Gen 6 with speeds up to 64Gbps per lane and up to 16 bonus PCIe Gen4 lanes. The 1P config supports up to 128 lanes of PCIe Gen 6 with 8 bonus PCIe Gen 4 lanes.
In the comparison chart, we can see that the socket sizing is different; it is smaller on SP8. The Max TDP is also different; SP7 is up to 600W max TDP, while SP8 is up to 400W max TDP. Overall memory bandwidth is down, but interestingly there is an increase in PCIe Gen 6 lanes and improved bandwidth for I/O.
There will also be a 6th Gen AMD EPYC “Verano” server CPU as well, with up to 6x CCDs. This is based on a 32 Core Zen 6c CCD or a 12 Core Zen 6 CCD. The Verano CPU supports and uses LPDDR5X instead at up to 8533MT/s and 24Ch memory at that. It supports up to 192 Zen 6c cores and 72 Zen 6 cores.
AMD EPYC 9006 “Venice” Platform Advancements
AMD has improved the entire platform for AMD EPYC 9006. There are a multitude of different memory configurations supported. DDR5 MRDIMM Gen2, DDR5 RDIMM, LP5X SOCAMM2, CXL 3.1, and MEXT. With DDR5 MRDIMM Gen2 JEDEC standard 12800 Gen2 support, up to 16Ch on SP7 or 8Ch on SP8 and up to 1.6TB/s of bandwidth. With DDR5 RDIMM support up to DDR5-8000, and 16Ch on SP7 and 8Ch on SP8. PCI Express 6.0 is supported, with up to 64GT/x PCIe Gen 6 links.
In a nutshell, Venice is for RDIMM/MRDIMM platforms, and Verano is the LPDDR variant and great for host nodes. For Agenc CPU server sandboxes, Venice can support up to 256 cores for high core counts at low power. For general-purpose CPU servers, you’ve got Venice on SP7 for high performance and high density, Venice on SP8 for balanced performance and power, and Venice-X for technical compute & HPC.
AMD EPYC 9006 Venice Rollout
With all of this, AMD can deliver the EPYC Venice 6th Gen CPUs for platforms across a wide variety of servers and needs. Venice 9006 on SP7, Venice 9006 on SP8, Venice-X 9006X on SPy, and Verano 9006 LP. Today, Venice 9006 on SP7 is shipping, and the rest will be ready across 2027.
Looking at the roadmap, 6th Generation EPYC “Venice” is an upgrade over 5th Generation EPYC “Turin”. This is a move from Zen 5/5c to Zen 6/6c. This new generation is the first to 2nm and 512 Threads, the first to JEDEC MRDIMM, and the first to x86 PCIe Gen 6.
AMD even outlines its future plans with 7th-generation EPYC “Florence” based on Zen 7/7c coming in 2028 on a next-gen processor node, AI compute extensions, and next-gen memory. AMD even brings this out further, showing us that there will be an 8th-generation EPYC “Ravenna” family based on Zen 8 coming in 2030!
Final Points
AMD is launching its AMD EPYC 9006 6th Generation “Venice” CPUs. As is typical for AMD, it all starts on the server side with CPUs, before the desktop CPUs and platform is launched. In this way, we kind of get a ‘sneak peek’ at what the potential for the next generation desktop could look like. We get to see a lot of information about the core architecture of Zen 6 itself, and potential configurations and SKUs. We also get a good look at what AMD is launching on the server side, and the innovations it is making for server platforms of all types, and the improvements over the previous generation.
In terms of EPYC itself, AMD is really kicking it up a notch in terms of sheer core count. Based on a 2nm process, AMD is packing a lot of cores into CCDs here. We’ve got the Zen 6c cores able to be packaged into 32 Core CCDs, and Zen 6 able to be packaged into 12 Core CCDs. This allows up to a total of 256-Core/512-Thread Zen 6c Cores, or 96-Core/192-Thread Zen 6 Cores.
That’s just a lot of cores in a single CPU package. Combine that with the SP7 and SP8 sockets, and improvements in power and communication, and it’s very impressive. AMD supports a wide variety of memory configurations, and some very high-bandwidth and efficient designs. AMD is also going to support PCIe 6.0; yes, PCIe Gen 6 is supported on the server side, with a lot of potential for I/O. We even learned that AMD is going to make a Venice-X 3D V-Cache variant.
Looking at the Zen 6 architecture, we see some great improvements that look like it will make a difference. Overall, we are seeing larger caches, better branch prediction, larger schedulers and store queues, and improved bandwidth and latency. One of the largest improvements if or course the move from 16 cores in the complex up to 32 with Zen 6c, and 8 cores in the complex with Zen 5 now up to 12 cores in the complex with Zen 6. In addition, the maximum frequency for Zen 6 Venice is a frequency improvement as well from 5GHz up to 5.3GHz. With the core increase comes the potential for improved cache capacities.
Keep this in mind, however: while these are the configurations possible for the server, that does not mean it will all be coming to the desktop PC side of things. This basically shows us the potential that is there with Zen 6, and what AMD could do on the desktop, if it were so inclined with Zen 6. I think the most exciting thing (that has been rumored, and may be true) is that we will see a core increase per complex or CCD with Zen 6 on the desktop.
We can see that AMD does have a 12-core-per-CCD configuration with Zen 6 on the server side. Will they bring that configuration down to the desktop? Will they launch a 24-Thread/48-Thread CPU on the desktop? Well, the potential is there for sure, so we will have to wait and see, but they could, and that’s the interesting part. All of this is very exciting, and we are in high anticipation of what AMD has in store for Zen 6 on the desktop. It looks like they’ve got the server side beat.
Additional Slides
AMD EPYC 9006 “Venice” Embedded
AMD EPYC “Venice” MEXT
AMD EPYC “Venice” HPC
Discussion
Join Discussion →No replies yet. Be the first to reply on the forum.