Hot Chips has published its schedule of programming for this year’s show, and with it comes the news that AMD and Intel will both be attending to share new details about some of its next-generation processors, including Zen 5 and 16th Gen “Lunar Lake” products. The news comes a few days after rumors of Zen 5 and Zen 6’s core configurations began circulating online; CCD configurations of up to 32 cores have been teased.
Event highlights for Hot Chips 2024 (August 26–27) include:
- AMD Next Generation “Zen 5” Core (Brad Cohen and Mike Clark, AMD)
- Lunar Lake: 16th Gen Intel Core processor (Arik Gihon, Intel)
- Snapdragon X Elite Qualcomm Oryon CPU: Design & Architecture Overview (Gerard Williams, Qualcomm)
- NVIDIA Blackwell GPU: Advancing Generative AI and Accelerated Computing (Ajay Tirumala and Raymond Wong, NVIDIA)
- AMD Instinct MI300X Generative AI Accelerator and Platform Architecture (Alan Smith and Vamsi Krishna Alla, AMD)
Alleged next-gen Zen details:
- “Zen 5C: Up To 12 CCDs (EPYC) / 16 Cores Per CCD / 1 CCX per CCD = Up To 192 Cores”
- “Zen 4C: Up To 8 CCDs (EPYC) / 16 Cores Per CCD / 2 CCX per CCD = Up To 128 Cores”
- “Zen 5: Up To 16 CCDs (EPYC) / 8 Cores Per CCD / 1 CCX per CCD = Up To 128 Cores”
- “Zen 4: Up To 12 CCDs (EPYC) / 8 Cores Per CCD / 1 CCX per CCD = Up To 96 Cores”
The original word from insiders @InstLatX64 and @Kepler24:
So then…
— 포시포시 (@harukaze5719) May 18, 2024
Zen 5 = 8C per CCD / Up to 128C
Zen 5c = 16C per CCD (but 1 CCX insted 2 in Zen4c) / Up to 192C
Zen 6 = 32C per CCD / Up to 256C
confirmed?
Zen6 has three CCDs, 8C/16C/32C.
— Kepler (@Kepler_L2) May 18, 2024
From a report:
[Zen 6] would include 8 cores per CCD, 16 cores per CCD, and up to 32 cores per CCD. With 16 cores per CCD, you can get up to 32 cores on a dual CCD part such as the Ryzen CPUs or up to 64 cores using the same CCD layout however it is likely that the highest core count die is based around the Zen 6C architecture & AMD tends to use the standard Non-C dies for its enthusiast parts.
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Discussion (7 replies)
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A 16-core, single-CCD part with X3D cache would be mighty interesting on the desktop!
Yeah I've been waiting for CCDs to have more than 8 cores per CCD, so that we can see more than just 8 cores having access to the 3D cache. Now another thing I wouldn't mind seeing is 3D cache on both CCDs.
agree on both counts, this half-CCD/cache thing was not the way, IMO
"DrezKill, post: 85501, member: 230" wrote:Yeah I've been waiting for CCDs to have more than 8 cores per CCD, so that we can see more than just 8 cores having access to the 3D cache. Now another thing I wouldn't mind seeing is 3D cache on both CCDs.
I agree with wanting an 'all or nothing' approach given that AMD went the software route for their mildly-heterogeneous architecture vs. say Intel with a hardware solution for their P- and E-cores.
Still think AMD needs to work the latency issue with multiple CCDs. They could address it directly, or they could improve operating system coordination for thread assignment, or come up with some other measure that is effective for software that will make use of the cores on multiple CCDs which is also sensitive to inter-core latency.
"Tsing, post: 85495, member: 5" wrote:Hot Chips
Kind of a poorly named conference, I think.
"LazyGamer, post: 85506, member: 1367" wrote:I agree with wanting an 'all or nothing' approach given that AMD went the software route for their mildly-heterogeneous architecture vs. say Intel with a hardware solution for their P- and E-cores.
Still think AMD needs to work the latency issue with multiple CCDs. They could address it directly, or they could improve operating system coordination for thread assignment, or come up with some other measure that is effective for software that will make use of the cores on multiple CCDs which is also sensitive to inter-core latency.
I would think the best way to do this is to oppose CCD scheduling to be akin to socket scheduling for multi socket systems. Then the OS could intelligently segregate load based on what is being ran across multiple CCX's more directly and not worry about thread scheduling between CCX's at all unless the load has more threads than a single CCX can provide.
AM5?
Discussion (7 replies)
Join Discussion →A 16-core, single-CCD part with X3D cache would be mighty interesting on the desktop!
Yeah I've been waiting for CCDs to have more than 8 cores per CCD, so that we can see more than just 8 cores having access to the 3D cache. Now another thing I wouldn't mind seeing is 3D cache on both CCDs.
agree on both counts, this half-CCD/cache thing was not the way, IMO
I agree with wanting an 'all or nothing' approach given that AMD went the software route for their mildly-heterogeneous architecture vs. say Intel with a hardware solution for their P- and E-cores.
Still think AMD needs to work the latency issue with multiple CCDs. They could address it directly, or they could improve operating system coordination for thread assignment, or come up with some other measure that is effective for software that will make use of the cores on multiple CCDs which is also sensitive to inter-core latency.
Kind of a poorly named conference, I think.
I would think the best way to do this is to oppose CCD scheduling to be akin to socket scheduling for multi socket systems. Then the OS could intelligently segregate load based on what is being ran across multiple CCX's more directly and not worry about thread scheduling between CCX's at all unless the load has more threads than a single CCX can provide.
AM5?