An AMD exec has officially revealed the launch date for the long-awaited Ryzen 9 flagship processors featuring 3D V-cache technology. AMD Senior Vice President and General Manager Jack Huynh has announced that the two processors based on the Zen 5 “Granite Ridge” architecture will launch on March 12. The 16-core/32-thread 9950X3D will be priced at $699 with the 12-core/24-thread 9900X3D priced at $599, echoing similar pricing of their 7950X3D/7900X3D predecessors and confirming earlier rumors.
The world's best processor for gaming and content creation is almost here.
— Jack Huynh (@JackMHuynh) March 7, 2025
Available starting March 12th
Ryzen 9 9950X3D – $699
Ryzen 9 9900X3D – $599
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Both processors are known to feature 2nd-gen 3D V-cache technology which has the cache located beneath the dual CCDs. By placing the CCDs at the top of the package, cooling potential is increased which has also allowed these X3D parts to have virtually the same clock speeds as their non-X3D counterparts. However, it has been previously revealed that only one CCD has access to the 3D V-Cache and as such gaming performance is expected to be similar to the Ryzen 7 9800X3D. However, these CPUs ought to excel in tasks or games that can take advantage of extra cores and threads along with their added 3D V-Cache technology. Per Jack Huynh, “The world’s best processor for gaming and content creation is almost here.”
Ryzen 9 9950X3D and 9900X3D Specifiactions
AMD already confirmed specifications for its Ryzen 9 9950X3D and 9900X3D processors ahead of CES 2025.
| Model | Cores/Threads | Boost4 / Base Frequency | Total Cache | PCIe | TDP |
| AMD Ryzen 9950X3D | 16C/32T | Up to 5.7 / 4.3 GHz | 144 MB | Gen 5 | 170W |
| AMD Ryzen 9900X3D | 12C/24T | Up to 5.5 / 4.4 GHz | 140 MB | Gen 5 | 120W |
Discussion (4 replies)
Join Discussion →Call me when they make a dual 3D V-Cache CCD Ryzen.
I'd like that too but the cost to benefit wasn't there this go around.
I'm personally not seeing the benefit of dual 3D V-Cache dies period - I think populating the second die slot with say a Zen5c 12-core die would make more sense. At least then you'd have the 'natural' scheduling advantage of having the second, non-3D V-Cache die being slower, while also gaining the advantage of having even more cores.
As I have pointed out before, my use case is very specific. It's for certain Primegrid sub-projects that have tasks that use more than 32MB L3 cache or even sub-projects that use more than 16MB of L3 cache where you could run two tasks on the same CCD if you had more than 32MB of L3.
Highly, highly specific. I know. It's why I've been considering buying an AMD EPYC 9684X setup.
Finding large prime numbers is fun.