Unofficial AMD X570 Chipset Block Diagram Surfaces on Chiphell

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An unofficial block diagram of the AMD X570 chipset has emerged on the Chiphell forums. It confirms PCI Express 4.0 support, alluding to a total of 24 lanes (or 28, if the additional southbridge is considered). Sixteen are reserved for GPUs, while four are allocated to M.2. The remaining lanes connect the CPU and chipset.

With PCIe 4.0, the chipset-processor interconnect gets twice the bandwidth compared to previous designs (16 GT/s, as opposed to PCIe 3.0’s 8 GT/s). On the SATA front are six 6 GB/s ports, while USB options comprise four 2.0 ports, four 3.0 ports, and two 3.1 ports.

AMD X570 overcomes the greatest shortcoming of the previous-generation X470 “Promontory” chipset – downstream PCIe connectivity. The X570 chipset appears to put out 16 downstream PCI-Express gen 4.0 lanes. Two of these are allocated to two M.2 slots with x4 wiring, each, and the rest as x1 links. From these links, three are put out as x1 slots, one lane drives an ASMedia ASM1143 controller (takes in one gen 3.0 x1 and puts out two 10 Gbps USB 3.x gen 2 ports); one lane driving the board’s onboard 1 GbE controller (choices include Killer E2500 or Intel i211-AT or even Realtek 2.5G); and one lane towards an 802.11ax WLAN card such as the Intel “Cyclone Peak.” Other southbridge connectivity includes a 6-port SATA 6 Gbps RAID controller, four 5 Gbps USB 3.x gen 1 ports, and four USB 2.0/1.1 ports.


Tsing Mui
News poster at The FPS Review.

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